As semiconductor design continues to advance, radio frequency (RF) functional blocks are increasingly being fabricated utilizing integrated passive device (IPD) technology in which passive components, such as resistors, capacitors, inductors, couplers, transformers and/or antennas, for example, are fabricated over a dielectric layer formed on a substrate. Because silicon substrates are extensively used in the integrated circuit (IC) industry, there are substantial cost advantages to implementing IPD processes on silicon. However, the relatively low resistivity of bulk silicon substrates introduces undesirable RF losses through coupling paths within the substrate.
A conventional method of controlling such RF losses uses an insulating layer to isolate the substrate from the signal-carrying conductive layers. Unfortunately, the use of such insulating layers results in charge accumulation at the interface between the silicon substrate and the overlying insulating layer. This charge accumulation forms a parasitic conduction layer (PCL) at the interface. The performance of the IPD is compromised by a parasitic coupling between the relatively low resistivity PCL and overlying conductors. This performance degradation may take the form of increased power loss through the IPD or decreased linearity of the IPD itself.
One method of avoiding formation of the PCL is by using a fully insulating substrate, such as quartz or sapphire. However, quartz and sapphire substrates are considerably more expensive than bulk silicon substrates and are not easily integrated into silicon manufacturing. Silicon-on-insulator (SOI) technologies having a trap-rich layer under the base oxide may also be utilized to mitigate the PCL. However, SOI wafers are also considerably more expensive than bulk silicon substrates.